1. Field of the Invention
The present invention relates generally to methods for forming gate dielectric layers within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming multiple gate dielectric layers with multiple thicknesses within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates over which are formed patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor integrated circuit microelectronic fabrication functionality levels have increased, it has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses. Within the context of the present invention, gate dielectric layers are intended as dielectric layers which are formed directly upon silicon semiconductor substrates, whether or not they are employed within field effect transistor (FET) devices, although gate dielectric layers are most typically employed within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. Similarly, although gate dielectric layers within semiconductor integrated circuit microelectronic fabrications are most commonly formed employing thermal oxidation methods, gate dielectric layers within semiconductor integrated circuit microelectronic fabrications may also be formed employing various combinations of thermal oxidation methods, deposition methods and nitridation methods.
It has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses insofar as the functional requirements and operational requirements of the pluralities of semiconductor devices formed within the semiconductor integrated circuit microelectronic fabrications often demand the plurality of gate dielectric layers having the plurality of gate dielectric layer thicknesses. For example and without limitation, within embedded semiconductor integrated circuit microelectronic fabrications (i.e., semiconductor integrated circuit microelectronic fabrications which perform both a logic function and a memory function), it is common to employ comparatively thin gate dielectric layers within field effect transistor (FET) devices which perform the logic function, such as to enhance operating speed of the field effect transistor (FET) devices which perform the logic function, while employing comparatively thick gate dielectric layers within field effect transistor (FET) devices which perform memory functions or other peripheral functions, wherein the field effect transistor (FET) devices which perform the memory function or other peripheral function are subject to comparatively high operating voltages.
While it is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, and often unavoidable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, forming within semiconductor integrated circuit microelectronic fabrications such semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses is not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses with enhanced manufacturability of the semiconductor integrated circuit microelectronic fabrications.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, with enhanced manufacturability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses, pluralities of semiconductor devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Barsan et al., in U.S. Pat. No. 5,672,521 (a method which employs implanting into a first region of a silicon semiconductor substrate a dose of a dopant which enhances thermal oxidation of the silicon semiconductor substrate and implanting into a second region of the silicon semiconductor substrate a dose of a nitrogen dopant which inhibits thermal oxidation of the silicon semiconductor substrate, such that upon thermal oxidation of the silicon semiconductor substrate including the first region, the second region and an unimplanted third region there is formed upon the silicon semiconductor substrate a gate dielectric layer having three thickness regions); (2) Chwa et al., in U.S. Pat. No. 6,147,008 (a method which employs implanting through a gate dielectric layer formed upon a silicon semiconductor substrate a dose of a nitrogen implanting ion which inhibits thermal oxidation of the silicon semiconductor substrate and then patterning the gate dielectric layer to form a patterned gate dielectric layer which leaves exposed implanted and unimplanted portions of the silicon semiconductor substrate, prior to thermally oxidizing the silicon semiconductor substrate to reform a gate dielectric layer having three thickness regions); and (3) Balasubramanian et al., in U.S. Pat. No. 6,235,591 (a sequential thermal annealing method for forming differential gate oxide layer thicknesses within semiconductor integrated circuit microelectronic fabrications with enhanced reliability by employing a bilayer sacrificial mask layer formed of other than a photoresist material).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods for forming within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, with enhanced manufacturability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced manufacturability.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a semiconductor substrate. To practice the method of the present invention, there is first defined a sequential and repetitive thermal oxidation and partial stripping method for forming upon a semiconductor substrate a plurality of gate dielectric layers having a maximum numbered plurality of differing thicknesses formed employing a corresponding maximum numbered plurality of thermal oxidation process steps. There is then sequentially and repetitively thermally oxidized and partially stripped the semiconductor substrate to form thereupon the plurality of gate dielectric layers having less than the maximum numbered plurality of differing thicknesses formed employing less than the corresponding maximum numbered plurality of thermal oxidation process steps. Within the present invention, there is also supplementally thermally annealed the semiconductor substrate to compensate for forming thereupon the plurality of gate dielectric layers having less than the maximum numbered plurality of differing thicknesses formed employing less than the corresponding maximum numbered plurality of thermal oxidation process steps.
Within the present invention, after having fabricated the semiconductor substrate while supplementally thermally annealing the same to thermally compensate for having formed thereupon the plurality of gate dielectric layers having less than the maximum numbered plurality of differing thicknesses formed employing less that the corresponding maximum numbered plurality of thermal oxidation process steps, there may be formed within and upon the semiconductor substrate a series of microelectronic devices while employing the plurality of gate dielectric layers.
There is provided by the present invention a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced manufacturability.
The present invention realizes the foregoing object by first defining a sequential and repetitive thermal oxidation and partial stripping method for forming upon a semiconductor substrate a plurality of gate dielectric layers having a maximum numbered plurality of differing thicknesses formed employing a corresponding maximum numbered plurality of thermal oxidation process steps. Similarly, the present invention then provides for sequentially and repetitively thermally oxidizing and partially stripping the semiconductor substrate to form thereupon the plurality of gate dielectric layers, but having less than the maximum numbered plurality of differing thicknesses formed employing less than the corresponding maximum numbered plurality of thermal oxidation process steps. Finally, the present invention provides for supplementally thermally annealing the semiconductor substrate to compensate for forming thereupon the plurality of gate dielectric layers having less than the maximum numbered plurality of differing thicknesses formed employing less than the corresponding maximum numbered plurality of thermal oxidation process steps. Within the present invention, the supplemental thermal annealing provides the semiconductor substrate with a uniform aggregate thermal exposure such that, for example and without limitation, device performance within the semiconductor substrate may be uniformly effected and modeled independently of a number of thermal oxidation process steps to which the semiconductor substrate is exposed.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering and specific process limitations to provide the present invention. Since it is thus at least in part a specific process ordering and specific process limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.